ACE Research and Development

ACE is an active participant on the European innovation scene, collaborating in ambitious projects with numerous partners in communities such as HiPEAC, CATRENE, ARTEMIS, where compiler technology plays a pivotal role. We have significant R&D experience and are familiar with the process and hurdles encountered when commercializing and exploiting the R&D that such industrial-academic collaboration of EU projects generates.

The R&D below illustrates the breadth of our team's involvement in the compiler technology ecosystem. As a small- and medium-sized enterprise, ACE uses EU projects to effect significant improvements in CoSy. Working closely with project partners we are able to experiment in meeting the demands imposed by new applications and system architectures on compiler technology. In addition to undertaking R&D work in these projects, ACE supplies training, support and mentoring in CoSy's use. We also like to aid spin-offs and frequently have interns from partners on-site.

CoSy used as compilation vehicle for new manycore reconfigurable architecture

The latest trends in chips include the combination of 3D stacking, heterogeneous multi/manycore and reconfigurability. A recurring challenge with utilizing the hardware provided by such technologies is the programming model. ACE has joined an industrial and academic consortium named FLEXTILES that will further improve the programming efficiency and reduce the development costs. ACE's focus in the project is on the compilation of stream-based applications onto multicore reconfigurable architectures. The FLEXTILES project would appreciate you filling in their survey.

Similarly, ACE contributed within the SMECY project (Smart Multicore Embedded SYstems) research concerning stream-based models employed to reach better performance in parallelizing audio and video applications. ACE has also improved CoSy optimization technology to improve the performance of embedded applications and systems used in SMECY.

CoSy technology as parallelization cornerstone

ACE provided its expertise in compilation and complex system designs to other research partners. HEAP's goal was to steer cache coherence protocol directly from the application using program directives. CoSy was the enabling technology used to trace an application's memory footprint. This profiling of parallelization patterns enables applications to be tuned manually but is also feasible for such tooling to provide suggestions on how to address potential issues.

CoSy provides a new cornerstone to end-users in the form of the aspect oriented programming paradigm. This core technology was utilized in an innovative manner within the project REFLECT. The CoSy compiler technology interprets these aspects to allow high-level control of the hardware design from the application code.

ACE is interested in exploring language extensions and annotations to describe, enable and implement optimizations and code transformations to map C application code fragments to particular architecture components. Within ASAM this compiler technology was used in the context of design space exploration for heterogeneous multi-processor embedded systems. The collaboration aimed to define a new unified design methodology, as well as, related automated synthesis and prototyping tool-chains. The new design environment allows rapid exploration of the high-level algorithm and architecture design spaces, as well as, an efficient automation of the final system synthesis, and in consequence, quick development of high-quality designs.

Our research team is investigating the adaption of many-core C extensions and thread-based programming models in solving programmability challenges of heterogeneous hardware/software systems. The CoSy framework offers a valuable platform for experiments using scalable and customizable whole system analysis and optimizations. This technology was employed within the project COBRA. The focus was on Hardwired SoC architectures that suffer from a lack of flexibility regarding market evolution, resulting in an excessive design cycle time and increased cost. The objective of COBRA was to develop and experiment an open, flexible and high performance platform by substituting heterogeneous hardware/software subsystems by a regular array of processors. The platform was driven by telecom, video and multimedia benchmark applications.

Previous R&D involvements in European projects

Apple-CORE - Architecture Paradigms and Programming Languages for Efficient programming of multiple CORES

MESA - Multi-processor embedded systems architectures

NEVA - Networks on Chips Design driven by Video & Distributed Applications

TSAR - Tera-Scale ARchitectures


Image courtesy of KROMKRATHOG/

HiPEAC, CATRENE, ARTEMIS, The EU commission - FP7 framework.