Philips Semiconductors secures license for ACE's CoSy Compiler Technology
ACE Press Release
Philips Semiconductors secures license for ACE's CoSy Compiler Technology to develop C-compilers for embedded architecture (R.E.A.L.) DSP cores.
San Jose, California, USA 30 September, 1997
In a licensing agreement with ACE Associated Computer Experts bv, Philips Semiconductors has gained access to a powerful compiler platform (CoSy) for its advanced in-house DSP (Digital Signal Processor) cores whose potential performance can now be fully exploited. One of the first aims under the agreement will be to realise an ANSI-C compiler. This will be expanded later with native DSP extensions (DSP-C language). ACE will also provide extensive supporting expertise.
For several years, the increasing complexity of processor and hardware architectures has opened up a performance gap between hardware and software that has left compiler writers struggling to keep pace with chip designers. With multiple memory spaces, specific instructions and dedicated register sets, advanced DSPs such as Philips Semiconductors' R.E.A.L.* family for audio, speech, telecom and multimedia applications present increasingly difficult target architectures for efficient C-compilation. Moreover, owing to certain inherent inadequacies, classical sequential-pass compilers can never produce fully optimized code for such state-of-the-art DSP architectures. Additionally, since assembler-level programming is time-consuming, error-prone, not portable between processor cores, and difficult to access by other programmers, a move to C-level entry is desirable.
The increase in complexity and internal parallelism of processors (RISC, DSP, multi-issue and multi-pipeline technologies) is making hand-crafted optimal code generators increasingly costly, and ultimately not cost effective. Realising this, ACE Associated Computer Experts bv, The Netherlands, has since 1988 moved completely to generator-based technology. In this technology, powerful generators produce, for example, code selectors, schedulers, register allocators and optimizers from detailed descriptions that reflect the working, parallelism and timing of the processor architecture.
At the heart of ACE's new generation of compilers is the CoSy parallel Compilation System in which a large number of compiler phases interact in parallel to produce optimal code-generation strategies. Providing significant design flexibility as well as reducing the time-to-market of the resulting embedded-software ASICs, CoSy has a clear potential to provide a quick return on investment. A radical approach to compilation going far beyond the classical, sequential-pass method, CoSy has already proved effective in the high-performance computing market. It will provide Philips with arguably the best tool currently available for developing optimized C-compilers for its proprietary DSP architectures in the shortest time.
Philips Semiconductors, a division of Philips Electronics NV, headquartered in Eindhoven, The Netherlands, is the ninth largest semiconductor supplier in the world. Philips Semiconductors' innovations in digital audio, video, and mobile technology position the company as a leader in the consumer, multimedia, and wireless communications markets. Sales offices are located in all major markets around the world, and are supported by regional customer application labs.
* R.E.A.L.: Reconfigurable Embedded Architecture Low-cost/Low-power
Philips Semiconductors and DSP-backgrounder to the ACE CoSy announcement
Philips Semiconductors is an acknowledged leader in the design of DSP architecture.
The company has developed two generations of embedded DSP cores for audio, speech, telecom, and multimedia applications:
- 1st generation EPICS used in DECT/ABC products (using the IC: PCD5091) and in car DSP/car audio products (using the IC: SAA7701).
- 2nd generation REAL DSP technology announced recently which features reconfigurable memory modules and peripherals, and can be extended with application-specific modules, making a family of ASIC DSP cores (IC type numbers still to be announced). A high-performance and a low-cost version of the REAL DSP core are available.
Philips Semiconductors' in-house cores are primarily for products aimed at high-volume consumer markets. Such cores are therefore driven by cost, time-to-market and power considerations, and by system integration constraints. With assembler programming having reached technical maturity for such markets, there are several arguments to move towards C-level entry of (embedded) application software. This would have the following benefits:
- higher programmer productivity, so shorter time-to-market
- higher level of re-use and portability between similar types of core
- use of and access to C application libraries
- OEM customers could program their own embedded software at C level.
Though C-level entry is generally beneficial, compilation constraints such as the embedded software code size, and the functional speed have in the past limited the performance of C-compilation. In addition, DSPs are well-known as difficult target architecture for efficient C-compilation owing to architecture characteristics such as multiple memory spaces, dedicated hardware and dedicated register sets. Traditionally, DSPs have not been successfully supported by C-compilers, especially as C-compiler constraints were not taken into account during the design of DSP architectures. During the development of Philips' REAL DSP architecture, these constraints have been taken into account - the hardware and software was co-designed and architecture and support tools (HL compiler) developed in parallel. This is why an in-house compiler platform (such as that secured from ACE) is required instead of subcontracting the compilation to an external tool vendor.
Under the new contract between Philips Semiconductors and ACE, the first aim is to realise an ANSI-C compiler. This will be extended later with native DSP extensions (DSP-C language).
CoSy is a registered trademark of ACE Associated Computer Experts bv