Osaka University Selects CoSy® compiler development system from ACE Associated Compiler Experts bv for PEAS-III Research Project

ACE Press Release

Amsterdam, The Netherlands 17 July, 2000

Hardware/Software Co-Design, compiler generation for flexible architectures key selection criteria

The latest PEAS-III development project from Osaka University will utilize advanced compiler generation technology from ACE Associated Compiler Experts bv. ACE's CoSy compiler development system offers support for hardware/software co-design, especially for flexible architectures that allow a core to be adapted to meet the specific needs of the application domain. Osaka University expects that CoSy will be able to deliver a compiler generation system that easily exceeds the limits of their previous methodology, specifically in the area of hardware/software co-design.

The PEAS-III project (Practical Environment for ASIP Development, ASIP stands for Application Specific Instruction set Processor) has been on-going for ten years. In this third stage of development, the goal is to provide a methodology to develop application domain oriented processor cores quickly and efficiently, and to have a compiler generator for these dedicated processor cores. Osaka University believes the design methodologies and technologies developed under the PEAS-III project are crucial to system-on-chip (SoC) design in the coming years, especially for multimedia processing and communication applications. Processor cores designed using PEAS-III will be more suitable for corresponding target applications than conventional off-the-shelf processor cores, taking the tradeoff of area, performance, and power consumption into consideration.

Compiler retargeting plays a very important role for hardware/software co-design in several ways. First, a compiler for an abstract machine is used to profile application programs. Secondly, the retargetable compiler must be able to quickly and easily deliver new code for each candidate of processor core under investigation, in order to predict the performance of the candidate. Finally, once a targeted processor core design is fixed, the compiler generation system must deliver a dedicated compiler for quality code.

"Successful design space exploration relies upon quick turnaround with accurate results," said Masaharu Imai, director of the PEAS-III project and professor of VLSI System Design Laboratory at Osaka University. "Our development work requires the most advanced products, and CoSy has certainly demonstrated that it will meet our demands. Hardware/software co-design is a tricky process, but ACE has developed a product that supports the design flow."

Imai expects to have the first compiler generator aspect of the PEAS-III design project complete by mid-2001.

"The PEAS-III project is an excellent vehicle to showcase the true capabilities of the CoSy compiler development system," said Rob Kurver, managing director of ACE Associated Compiler Experts bv. "We are always pleased to participate in such efforts by an outstanding research institute. Their work will certainly aide the continuing evolution of the CoSy product."

The PEAS-III project has been performed for several years as collaborative research among academic institutes, including Osaka University, Shizuoka University, Tsuruoka College of Technology, Toyota Collage of Technology, and Nara Collage of Technology.

The PEAS-III project is sponsored by STARC (Semiconductor Technology Academic Research Center), a Japanese organization similar to SRC (Semiconductor Research Center) in the U.S. STARC was established in December 1995 by eleven major Japanese semiconductor companies, including Fujitsu, Hitachi, Matsushita, Mitsubishi, NEC, Oki, Rohm, Sanyo, Sharp, Sony and Toshiba in order to promote research and development collaboration between academia and industry. More information on the PEAS-III project can be found at and

ACE Associated Compiler Experts bv (a wholly owned subsidiary of ACE Associated Computer Experts, Amsterdam, The Netherlands) is a world leader in the production of compiler development tools. Its open CoSy compiler development platform gives compiler developers the ability to achieve a similar leading edge position in the construction of better and faster optimizing compilers for architectures ranging from 4-bit DSPs to 256-bit VLIW processors. CoSy also supports a wide range of programming languages including C, Fortran and Java.