The MMDSP+ core targets multimedia applications, particularly high-end audio. As Jean-Marc Gentit, architect of the MMDSP+ in ST's Telecom, Peripherals and Automotive group points out, "every last bit of processing performance you can squeeze out of an embedded DSP processor counts, because the spare MIPS that you generate allow your customers to implement the added features needed to differentiate their products in the market place." As a result, ST were not only optimizing for code size, but also for the minimum number of MIPS to execute specific audio codecs.
As a representative benchmark application, they chose the Enhanced Full Rate (EFR) codec developed for GSM cellular telephony, that is readily available as standard C source code, and widely accepted as a good test of a DSP's capabilities. They took CoSy out of the box and quickly generated a compiler that would perform this codec function using around 48 MIPS.

ST then set about adding their own optimization engines to CoSy, mainly to leverage advantage from their DSP architecture's vector and array handling capabilities. The first step in this process was to get a better understanding of how CoSy works, which was speedily achieved through a customized training course given by ACE's software engineers.

"We achieved 48 MIPS by compiling the standard source code for EFR codec, without doing any hand optimization, which is pretty good for an out-of-the-box solution." Jean Marc Gentit, architect of the MMDSP+ core in STMicroelectronics Telecom, Peripherals and Automotive group

"When we started to understand how CoSy works, what immediately impressed us was how clean and extendable its software architecture is," said Miguel Santana, head of the Embedded Software Development Tools department in ST's Central R&D group, which worked closely with the MMDSP+ team.
With much of ST's IP in optimization engine design already embodied in prototype compilers that the company had developed before starting to use CoSy, the ability to extract these optimization engines and retarget them for use in CoSy was of paramount importance.

"From our prototyping experience in the Central R&D group we had come to the realization that developing a highly efficient, fully validated, retargetable compiler environment from scratch takes around 50 man/years of effort," said Santana. "What ACE did was provide us with 45 of those man/years straight out of the box, on top of which our small team of specialists was able to add its optimization engine knowledge in around one year."

The result has been that the 48 MIPS of DSP processing initially required to execute the EFR codec has now been reduced to around 20 MIPS, which is considerably better than the 25 MIPS target that ST had set itself.
"With this number of MIPS, CoSy is generating compilers that are within 10% of the performance we think could be achieved by hand-crafted assembler code," said Gentit.

"The extreme modularity of the software significantly simplified the autonomous development of ST-specific optimizations on top of CoSy, and did so in very maintainable fashion." Miguel Santana, head of Embedded Software Development Tools department in STMicroelectonics Central R&D Group

The excellent results achieved by combining CoSy with ST's own optimization engines have enabled ST to develop a new hardware/software co-design methodology that allows new DSP architectures to be designed while taking into account the capabilities of the software compilation technology.
"We now design our hardware DSP architectures so that they make maximum use of the compiler's capabilities as well as meeting the run-time requirements of the application software," said Gentit. "This makes CoSy a very important part of our overall tool set."